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? 2002 microchip technology inc. ds21412b-page 1 TC3403 features ? 16-bit resolution at eight conversions per second, adjustable down to 10-bit resolution at 512 conversions per second 1.8v ? 5.5v operation, low power operating 280 a; sleep: 93 a four single-ended inputs with built-in multiplexer microport? serial bus requires only two interface lines uses internal or external reference automatically enters sleep mode when not in use v dd monitor and reset generator operational in shutdown mode early warning power fail detector, also suitable as wake-up timer operational in shutdown mode applications consumer electronics, thermostats, co monitors, humidity meters, security sensors embedded systems, data loggers, portable equipment medical instruments device selection table package type general description the TC3403 is a low cost, low power analog-to-digital converter based on microchip?s sigma-delta technol- ogy. it will perform 16-bit conversions (15-bit plus sign) at up to eight per second. the TC3403 is optimized for use as a microcontroller peripheral in low cost, battery operated systems. a voltage reference is included, or an external reference can be used. a v dd monitor with a reset generator provides power-on reset and brown- out protection while an extra threshold detector is suitable for use as an early warning power fail detector, or as a wake-up timer. the TC3403?s 2-wire microport? digital interface is used for starting conversions and for reading out the data. driving the sclk line low starts a conversion. after the conversion starts, each additional falling edge (up to six) detected on sclk for t 4 seconds reduces the a/d resolution by one bit and cuts conversion time in half. after a conversion is completed, clocking the sclk line puts the msb through lsb of the resulting data word onto the sdat line, much like a shift register. the part automatically sleeps when not performing a data conversion. theTC3403isavailableina16-pinpdipanda16-pin qsop package. part number package temperature range TC3403vpe 16-pin pdip (narrow) 0 cto+85 c TC3403vqr 16-pin qsop narrow) 0 cto+85 c 16-pin pdip 16-pin qsop 1 16 215 314 413 512 611 710 in4+ 89 in1+ in2+ v th ref in gnd a0 v dd pfo sdat ref ou t in3+ TC3403 sclk pfi reset a1 +1.8v low power, quad input, 16-bit sigma-delta a/d converter with a power fault monitor and microprocessor reset circuit
TC3403 ds21412b-page 2 ? 2002 microchip technology inc. typical application functional block diagram TC3403 controller sdat sclk a0 a1 reset pfo pfi ref out ref in v th in4+ in3+ in2+ in1+ i/01 i/02 i/03 i/04 rst i/05 i/06 v batt v batt v batt v batt v batt c1 0.1 f r1 130k r2 110k r3 390 c2 10 f r4 1m ? v dd r7 100k r6 100k v cc + + + + a0 TC3403 in2+ in3+ sdat ref in ref ou t sclk clock generator and control circuitry data shift reg. ? ? modulator 1 of 4 amux + ? + ? x2 conv done convclk dq set clr 1.193v v dd clkout start conv. dq set clr a1 in1+ + ? in4+ + ? pfo pfi + ? 1.205v reset delay timer + ? reset v th 1.205v gnd
? 2002 microchip technology inc. ds21412b-page 3 TC3403 1.0 electrical characteristics absolute maximum ratings* supply voltage ..................................................... 6.0v voltage on pins: pfo , reset .......................... (gnd ? 0.3v) to 5.5v input voltage (all other pins): .................................. (gnd ? 0.3v) to (v dd +0.3v) operating temperature range ................. 0c to 85c storage temperature ........................ -65c to +150c *stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. TC3403 dc electrical specifications electrical characteristics: t a = 25c and v dd = 2.7v, unless otherwise specified. boldface type specifications apply for temperatures of 0c to 85c. v ref = 1.25v, internal clock frequency = 520khz. symbol parameter min typ max unit test conditions power supply v dd supply voltage 1.8 ? 5.5 v i dd supply current, during data conversion ? 280 ? a i dd sleep supply current, sleep mode ? 93 115 at a =+25c ? 106 120 a accuracy (differential inputs) res resolution ? 16 ? bits inl integral non-linearity ? .0038 ? %fsr v dd =2.7v v os offset error ? ? 0.9 %fsr in+, in- = 0v v noise referred to input ? 60 ? vrms cmr common mode rejection ? 75 ? db at dc fse full scale error ? 0.4% ? %fs psrr power supply rejection ratio ? 75 ? db v dd =2.5vto3.5v inn v in input voltage ? ? v dd v note 1 absolute voltage range on inn gnd ? v dd v input bias current ? 1 100 na c in input sampling capacitance ? 2 ? pf r in differential input resistance ? 2.0 ? m ? note 2 ref in, ref out v ref ref in voltage range 0 ? 1.25 v i ref ref in input current ? 1 ? a v ref out ref out voltage ? 1.193 ? v ref sink ref out current sink capability ? 10 ? a ref src ref out current source capability 300 ? ? a note 1: differential input voltage defined as (v in +?v in -). 2: resistance from inn+ to inn- or inn to gnd. 3: @v dd =1.8v,i source 200 a.
TC3403 ds21412b-page 4 ? 2002 microchip technology inc. TC3403 ac electrical specifications sclk, a0, a1, enable v il input low voltage ? ? 0.3xv dd v v ih input high voltage 0.7xv dd ??v i leak leakage current ? 1 ? a sdat, reset ,pfo v ol output low voltage ? ? 0.4 v i ol =1.5ma v oh output high voltage (sdat) 0.9 x v dd ??vi source =400 a (note 3) v dd min minimum v dd for pfo , reset valid ? 1.1 1.3 a v th ,pfi v ccpfi pfi input voltage range 0 ? v dd v v th , pfi input current -0.1 .01 0.1 a v thr threshold (v th , pfi) ? 1.23 ? v threshold hysteresis ? 30 ? mv threshold tempco ? 30 ? ppm/c electrical characteristics: t a = 25c and v dd = 2.7v, unless otherwise specified. boldface type specifications apply for temperatures of 0c to 85c. v ref = 1.25v, internal clock frequency = 520khz. symbol parameter min typ max unit test conditions t 1 resolution reduction clock width 1 ? ? sec width of sclk (negative) t 2 resolution reduction clock width 1 ? ? sec width of sclk (positive) t 3 conversion time (15-bit plus sign) ? 125 ? msec 16-bit conversion, t a =25c (note 1) conversion time (14-bit plus sign) ? t 3 /2.0 ? msec 15-bit conversion conversion time (13-bit plus sign) ? t 3 /4.0 ? msec 14-bit conversion conversion time (12-bit plus sign) ? t 3 /7.8 ? msec 13-bit conversion conversion time (11-bit plus sign) ? t 3 /15.1 ? msec 12-bit conversion conversion time (10-bit plus sign) ? t 3 /28.6 ? msec 11-bit conversion conversion time (9-bit plus sign) ? t 3 /51.4 ? msec 10-bit conversion t 4 resolution reduction window ? t 3 /85.7 ? msec width of sclk t 5 sclk to data valid 1000 ? ? nsec sclk falling edge to sdat valid t 6 address setup 0 ? ? nsec address valid to sclk t 7 address hold 1000 ? ? nsec sclk to address valid hold t 8 acknowledge delay ? ? 1000 nsec sclk to sdat delay t 9 reset active timeout period ? t 3 *2 ? msec delay from por or brown-out recovery to reset =v oh t 10 pfo delay ? 25 ? sec pfi to pfo delay t 11 reset delay 5 ? 64 sec delay v th falling at 10v/msec to reset low note 1: nominal temperature drift is -2830ppm/c for temperature less than 25c and -1340ppm/c for temperatures greater than 25c . TC3403 dc electrical specifications (continued) electrical characteristics: t a = 25c and v dd = 2.7v, unless otherwise specified. boldface type specifications apply for temperatures of 0c to 85c. v ref = 1.25v, internal clock frequency = 520khz. symbol parameter min typ max unit test conditions note 1: differential input voltage defined as (v in +?v in -). 2: resistance from inn+ to inn- or inn to gnd. 3: @v dd =1.8v,i source 200 a.
? 2002 microchip technology inc. ds21412b-page 5 TC3403 2.0 pin descriptions thedescriptionsofthepinsarelistedintable2-1. table 2-1: pin function table pin no. (16-pin pdip) (16-pin qsop) symbol description 1 in1+ analog input. this is the positive terminal of a true differential input with the negative input tied internally to gnd. see section 1.0, electrical characteristics. 2 in2+ analog input. this is the positive terminal of a true differential input with the negative input tied internally to gnd. see section 1.0, electrical characteristics. 3 in3+ analog input. this is the positive terminal of a true differential input with the negative input tied internally to gnd. see section 1.0, electrical characteristics. 4 in4+ analog input. this is the positive terminal of a true differential input with the negative input tied internally to gnd. see section 1.0, electrical characteristics. 5 pfi analog input. this is the positive input to an internal comparator used as a threshold detector. the negative input is tied to an internal reference. 6v th analog input. this is the positive input to the internal comparator used to monitor the voltage supply. the negative input is tied to an internal reference. when v th falls below the internal reference, the reset generator drives reset low. see section 1.0, electrical characteristics. 7ref in analog input. the converter?s reference voltage is the differential between this pin and ground times two. it may be tied directly to ref out or scaled using a resistor divider. any user supplied reference voltage less than 1.25 may be used in place of ref out . 8 gnd ground terminal. 9ref out analog output. the internal reference connects to this pin. it may be scaled externally and tied to the ref in input to provide the converter?s reference voltage. care must be taken in connecting external circuitry to this pin. this pin is in a high impedance state during sleep mode. 10 sdat digital output (push-pull). this is the microport? serial data output. sdat is driven low while the TC3403 is converting data, effectively providing a ?busy? signal. after the conversion is complete, every high to low transition on the sclk pin puts a bit from the resulting data word on the sdat pin (from msb to lsb). 11 pfo digital output (open drain). this is the output of the internal threshold detector. when pfi is less than the internal reference, pfo is driven low. 12 reset digital output (open drain). this is the output of the v dd monitor reset generator. reset is driven low when a power-on reset or brown-out condition is detected. see section 1.0, ac electrical characteristics. 13 a1 digital input. controls analog multiplexer in conjunction with a0 to select one of the four input channels. this address is latched at the falling edge of the sclk, which starts an a/d conversion. a1, a0 = 00 = input 1; 01 = input 2; 10 = input 3; 11 = input 4. 14 a0 digital input. controls analog multiplexer in conjunction with a1 to select one of four input channels. this address is latched at the falling edge of the sclk, which starts an a/d conversion. a1, a0 = 00 = input 1; 01 = input 2; 10 = input 3; 11 = input 4. 15 sclk digital input. this is the microport? serial clock input. the TC3403 comes out of sleep mode and a conversion cycle begins when this pin is driven low. after the conversion starts, each additional falling edge (up to six) detected on sclk for t 4 seconds reduces the a/d resolution by one bit. when the conversion is complete, the data word can be shifted out on the sdat pin by clocking the sclk pin. 16 v dd power supply input.
TC3403 ds21412b-page 6 ? 2002 microchip technology inc. 3.0 detailed description the TC3403 has a 16-bit sigma-delta a/d converter. it has two differential inputs, an analog multiplexer, a v dd monitor with reset generator and an early warning power fail detector. see the typical application circuit and the functional block diagram. the key components of the TC3403 are described below. also refer to figure 3-5, a/d operational flowchart and the timing diagrams, figure 3-1, figure 3-2 and figure 3-3. 3.1 a/d converter operation when the TC3403 is not converting, it is in sleep mode with both the sclk and sdat lines high. an a/d con- version is initiated by a high to low transition on the sclk line at which time the internal clock of the TC3403 is started and the address value (a0 and a1) is internally latched. the address value steers the ana- log multiplexer to select the input channel to be con- verted. each additional high to low transition of sclk (following the initial sclk falling edge) during the time interval t 4, will decrement the conversion resolution by one bit and reduce the conversion time by one half. the time interval t 4 is referred to as the resolution reduction window. the minimum conversion resolution is 10-bits so any more than 6 sclk transitions during t 4 will be ignored. after each high to low transition of sclk, in the t 4 interval, the sdat output is driven high by the TC3403 to acknowledge that the resolution has been decre- mented. when the sclk returns high or the t 4 interval ends, the sdat line returns low (see figure 3-2). when the conversion is complete sdat is driven high. the TC3403 now enters sleep mode and the conversion value can be read as a serial data word on the sdat line. 3.2 reading the data word after the conversion is complete and sdat goes high, the conversion value can be clocked serially onto the sdat line by high to low transitions of the sclk. the data word is in two?s compliment format with the sign bit clocked onto the sdat line, first followed by the msb and ending in the lsb. for a 16-bit conversion the data word would consist of a sign bit followed by 15 magni- tude bits, table 3-1 shows the data word versus input voltage for a 16-bit conversion. note that the full scale input voltage range is (2 ref in ? 1lsb). when ref out is fed back directly to ref in ,anlsbis73 v for a 16-bit conversion, as ref out is typically 1.193v. figure 3-4 shows typical sclk and sdat waveforms for 16, 12 and 10-bit conversions. note that any com- plete convert and read cycle requires 17 negative edge clock pulses. the first is the convert command. then, up to six of these can occur in the resolution reduction window, t 4 , to decrement resolution. the remaining pulses clock out the conversion data word. table 3-1: data conversion word vs. voltage input (ref in = 1.193v) the sclk input has a filter which rejects any positive or negative pulse of width less than 50nsec to reduce noise. the rejection width of this pulse can vary between 50nsec and 750nsec depending on process- ing parameters and supply voltage. figure 3-1 and table 3-2 show information for deter- mining the mode of operation for the TC3403 by recording the value of sdat for sclk in a high, then low, then high state. for example, if sclk goes through a 1-0-1 transition and the corresponding values of sdat are 1-1-0, then the sclk falling edge started a new data conversion. a 0-1-0 for sdat would have indicated a resolution reduction had occurred. this is useful if the microcontroller has a watchdog reset or otherwise loses track of where the TC3403 is in the conversion and data readout sequence. the microcontroller can simply transition sclk until it ?finds? a start conversion condition. figure 3-1: sclk, sdat logic state diagram table 3-2: sclk, sdat logic state * note: the code x00 has a dual meaning: data transfer or busy converting. to avoid confusion, the user should send only the required number of pulses for the desired resolution, then wait for sdat to rise to 1, indicating conversion is complete before clocking sclk again to read out data bits. data word inn + ?inn-(volts) 0111 1111 1111 1111 2.38596 (positive full scale) 0000 0000 0000 0001 72.8 e -6 0000 0000 0000 0000 0 1111 1111 1111 1111 -72.8 e -6 1000 0000 0000 0001 -2.38596 (negative full scale) 1000 0000 0000 0000 reserved code ab c status 1 1 0 start conversion 0 1 0 resolution reduction x 1 1 data transfer x 0 0 data transfer or busy* sclk sdat a bc
? 2002 microchip technology inc. ds21412b-page 7 TC3403 figure 3-2: conversion and data output timing figure 3-3: reset and power fail timing sclk sdat t 4 t 1 t 2 t 3 t 8 t 8 d n-1 d n-2 d 0 (lsb) d n (msb) t 5 data conversion complete sleep mode a0, a1 start conversion and resolution control timing data output timing t 6 t 7 reset 0 v th 1.23 v dd reset generator timing t 9 t 11 power fail com p arator timin g 1.1 1.20 hysteresis time volts pfo 0 pfi 1.23 t 10 t 10 t 10 t 10 1.1 1.20 hysteresis time volts v dd v dd t 9 t 11 1.80
TC3403 ds21412b-page 8 ? 2002 microchip technology inc. figure 3-4: sclk and sdat waveforms for 16, 12 and 10-bit conversions sclk sdat t 3 a 16-bit data conversion, data word a5a5h sclk sdat 16-bit data conversion, long start pulse, data word 5a5ah > t 3 a data conversion complete sclk sdat 12-bit conversion, data word = ab3h sclk sdat t 3 g 10-bit conversion with "extra" data reduction clocks, data word = 3a4h data conversion complete data conversion complete data conversion complete t 3 e < t 4 < t 4
? 2002 microchip technology inc. ds21412b-page 9 TC3403 figure 3-5: a/d operational flowchart yes no yes no yes yes yes no no no yes yes no yes no por sleep sdat = high sclk hgh to low? power up analog, start convclk (= 0), start conversion, resolution = 2m (m = 16), latch input channel address (if applicable). sclk low to high transition? sdat = low convclk < 2 9 ? sclk high to low? a/d resolution > 2 10 ? reduce a/d resolution by 1-bit (m = m ? 1); sdat = high sdat = low convclk = 2m? (conversion done?) power down analog, conversion complete, sdat = high sclk high to low? sdat = dm; m = m ? 1 m 0? sdat = high internal reset sleep no
TC3403 ds21412b-page 10 ? 2002 microchip technology inc. 3.3 v dd monitor the TC3403 reset output is high impedance pro- vided the voltage at v th is greater than the internal voltage reference. this reference is approximately the same value as the voltage appearing at ref out .when v th is less than the internal reference, reset is pulled low. when v th rises above the internal reference voltage again, reset is held low for the reset active timeout period, t 9 , before being released. the reset output is ensured to be valid for v dd = 1.3v to 5.5v. when used to generate a power-on or brown-out reset, an external resistor network is required to divide the appropriate v dd threshold down to 1.23v at the v th input, (see the typical application circuit). for example, to generate a por for a v dd at 3v- 10%, then the values of r1 and r2 should be 137k ? and 115k ? respectively. since reset is an open drain, it can be wired-or?ed with another open drain or external switch if desired. 3.4 power fail detector the power fail detector is a comparator in which the inverting input is connected to the internal voltage reference. the non-inverting input is the pfi pin of the TC3403 and the pfo pin is the active low, open drain output. this comparator is suitable as an early warning fail or low battery indicator. in a typical application, where a voltage regulator is being used to supply power to a system, the power fail comparator would monitor the input voltage to the regulator while the v dd monitor would measure the output voltage of the regulator. both pfo and reset would drive interrupt pins of a microcontroller. thepowerfaildetectormaybeusedasawake-upor watchdog timer. the typical application circuit shows an rc network on pfi with the capacitor tied to a tristated c i/o pin. if r4 is 1 m ? and c2 is 10 f, t h e time constant is roughly ten seconds. the c resets the rc network by driving the i/o tied to pfi low and then tristating it. the rc network will ramp to 1.23v in roughly 9 seconds, assuming a v batt of 3.0v. with pfo tied to a c input or interrupt, the c will see a low to high transition on pfo when the voltage on pfi exceeds 1.23v. the pfo output is specified to be valid for v dd =1.3to5.5v.
? 2002 microchip technology inc. ds21412b-page 11 TC3403 4.0 packaging information 4.1 package marking information package marking data not available at this time. 4.2 taping forms component taping orientation for 16-pin qsop (narrow) devices pin 1 user direction of feed standard reel component orientation for tr suffix device w p package carrier width (w) pitch (p) part per full reel reel size 16-pin qsop (n) 12 mm 8 mm 2500 13 in carrier tape, reel size, number of components per reel and reel size
TC3403 ds21412b-page 12 ? 2002 microchip technology inc. 4.3 package dimensions .110 (2.79) .090 (2.29) .022 (0.56) .015 (0.38) .150 (3.81) .115 (2.92) .770 (19.56) .740 (18.80) .045 (1.14) .030 (0.76) .070 (1.78) .045 (1.14) .310 (7.87) .290 (7.37) .040 (1.02) .020 (0.51) .270 (6.86) .240 (6.10) .200 (5.08) .140 (3.56) .014 (0.36) .008 (0.20) .400 (10.16) .310 (7.87) 16-pin pdip (narrow) pin 1 10 max. dimensions: inches ( mm ) 8 max. pin 1 .157 (3.99) .150 (3.81) .196 (4.98) .189 (4.80) .012 (0.31) .008 (0.21) .010 (0.25) .004 (0.10) .069 (1.75) .053 (1.35) .010 (0.25) .007 (0.19) .050 (1.27) .016 (0.41) .244 (6.20) .228 (5.80) .025 (0.635) typ. 16-pin qsop (narrow) dimensions: inches (mm)
? 2002 microchip technology inc. ds21412b-page 13 TC3403 sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
TC3403 ds21412b-page 14 ? 2002 microchip technology inc. notes:
? 2002 microchip technology inc. ds21412b-page 15 TC3403 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, filterlab, k ee l oq ,microid, mplab,pic,picmicro,picmaster, picstart, pro mate, seeval and the embedded control solutions company are registered trademarks of microchip tech- nology incorporated in the u.s.a. and other countries. dspic, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, mxdev, picc, picdem, picdem.net, rfpic, select mode and total endurance are trademarks of microchip technology incorporated in the u.s.a. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2002, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
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